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Security verification simulator for fault analysis attacks  

 Masaya Yoshikawa1,Hikaru Goto2

*1, Meijo university, Email : dpa_cpa@yahoo.co.jp
2, Meijo university, Email : 123430017@ccalumni.meijo-u.ac.jp
 
Abstract .The advanced encryption standard (AES) is the most popular encryption standard in the world. Although the AES algorithm is theoretically safe, it has been recently reported that confidential information could be illegally revealed when the AES algorithm is used in electronic circuits. In particular, the menace posed by fault analysis attacks has become extremely serious. This study develops a software simulator to evaluate the vulnerability of a cryptographic circuit against fault analysis attacks in which multiple analytical methods are combined. Simulation results proved the validity of the proposed simulator.
 
Keywords : Security verification ; Software simulator ; Fault analysis attacks ; Cryptogram
 URL: http://dx.doi.org/10.7321/jscse.v3.n3.71  
 
 

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